This relates generally to phase-locked loop (PLL) circuits; and, more particularly, to PLL circuits including phase frequency detectors and charge pumps.
In phase-locked loop (PLL) circuits, a time discrete phase frequency detector is widely used in combination with a charge pump. The phase frequency detector circuit generates the UP and DOWN signal for the charge pump. The charge pump delivers a constant source or sink current with a pulsewidth that depends upon the input signals. The width of the current pulse is equal to the phase offset of the UP and DOWN signal, which also reflects the phase offset of the reference clock and feedback clock signal. The pulsewidth is also the time duration to charge or discharge the PLL filter capacitor. When the PLL circuit has acquired lock, the current pulse duration is very small and only a little switching noise (at the PLL update frequency) is seen at the control voltage of the voltage controlled oscillator (VCO) in the PLL circuit.
The width of the current pulse is not limited by the circuit. If there is a very high jitter on the input clock, or if there are missing clock pulses, the phase offset never becomes very low. The same is true for fractional-N PLL circuits. There will never be a zero phase offset due to the principle of the fractional division in the PLL feedback path. A high phase offset is unlikely, which is the reason for noise on the VCO control voltage, and therefore the output jitter. Noise caused by the charge pump current pulse can be reduced by decreasing the loop filter bandwidth and, therefore, the PLL bandwidth. However this is not possible or adequate for all PLL applications.
The invention has been devised with the foregoing in mind.